1. Field of the Invention
The present invention relates to technologies for low power consumption and high speed of a semiconductor memory.
The present invention also relates to a semiconductor memory having memory cells with capacitors, and more particularly to a technology for performing refresh of the memory cells internally and automatically.
2. Description of the Related Art
Semiconductor memories such as a DRAM typically use common address terminals to receive address signals as a row address and a column address separately, and perform read, write, or other operations. For example, a 64-Mbit DRAM having an 8-bit I/O (address space; 8 Mbits) uses two bank address terminals and twelve address terminals to receive a 12-bit row address signal and a 9-bit column address signal. This DRAM, for example, receives an active command and a row address signal (upper address) in synchronization with a first clock signal, and receives a read command and a column address (lower address) in synchronization with the next clock signal. Here, all the word lines corresponding to the row address are activated to read out the data retained in the memory cells. The read data is amplified by sense amplifiers. In this example, the activation of the word lines selects one out of 16 k memory regions so that data is rewrite of 4 k memory cells. Then, the memory cells to read/write data from/to are selected by the column address signal, followed by a read operation or a write operation.
Now, a rise in the number of bits of the row address signal can reduce the size of a memory region to be selected at a time, and decrease the number of word lines to be activated simultaneously. The power consumption during read and write operations depends on the number of word lines to be activated as well as the number of sense amplifiers to be operated in accordance with the activation of the word lines. Thus, the greater the number of bits of the row address signal is, the lower the operating power consumption becomes.
For example, if the above-mentioned DRAM has two bank address terminals and thirteen address terminals to receive a 13-bit row address and an 8-bit column address, the number of word lines to be activated at a time will be cut by half, with a reduction in power consumption.
The greater number of bits of the row address signal, however, increases the number of terminals on the package, which makes the package larger in outside dimensions. As a result, the system board to mount the DRAM on comes to drop in parts mounting density. The parts mounting density can also be lowered by a rise in the number of lines on an address bus and an increase in the area of patterned wiring on the system board. The increased number of address terminals also leads to a greater chip size.
Meanwhile, a great number of DRAMs are used not only in mainframes and personal computers but also in consumer appliances. Generally, most DRAMs to be mounted on consumer appliances have only to operate at several tens of megahertz. Conventional DRAMs, however, have not been developed specifically for consumer appliances. Therefore, the consumer appliances to mount DRAMs on have had to adopt high-speed DRAMs targeted for computers. DRAMs of this type are developed for high-speed operations, and are often high in power consumption. In the fields of battery-driven consumer appliances such as cellular phones and digital cameras, DRAMs of low power consumption have been hoped for.
DRAM memory cells store information by having their capacitors charged. This requires that DRAM-mounted systems refresh memory cells at predetermined intervals to maintain the information written in the memory cells. Read and write operations to memory cells cannot be performed during refresh operations. This means the tendency of the above-mentioned systems to drop in I/O bus occupation rate. In particular, concerning DRAMs to be operated at lower frequencies which have been hoped for in the fields of consumer appliances and the like, there has been made no proposal for optimizing refresh operations thereof to improve the I/O bus occupation rate.
An object of the present invention is to reduce the power consumption of a semiconductor memory.
Another object of the present invention is to optimize the refresh operations of memory cells in a DRAM being operative at a low frequency, for the sake of improving an I/O bus occupation rate.
Still another object of the present invention is to reduce the time taken for the supply of a command to the completion of a read or write operation in the semiconductor memory being operative at a low frequency.
According to one of the aspects of the present invention, a semiconductor memory receives a plurality of commands in succession and performs a memory operation to read/write data from/to memory cells in accordance with the combination of these commands. Here, a word line for controlling transfer switches of the memory cells is activated after the reception of one of the commands except the first command. This allows a control circuit for activating the word line to be operated at a frequency lower than heretofore, which reduces the power consumption.
There is a sufficient period between the supply of the first command and the activation of the word line. Therefore, this period can be utilized to operate internal circuits without being recognized from exterior. The internal circuits include, for example, a refresh control circuit for automatically performing a refresh operation of the memory cells, and a self-test circuit for checking circuit functions.
According to another aspect of the present invention, address signals for designating the memory cells to be operated are supplied along with the commands. The word line is activated based on the address signal supplied along with the first command as well as part of the address signal supplied along with at least one of the commands except the first command. Activating the word line by using more address signals than heretofore can reduce the number of word lines to be activated simultaneously. In other words, the memory regions to be selected by these address signals become smaller. As a result, the scale of the circuits to be operated for memory operations can be decreased for a reduction in power consumption.
According to another aspect of the present invention, the word line includes a main-word line and a plurality of sub-word lines branching off from this main-word line. The sub-word lines are connected to the transfer switches of the memory cells. The main-word line corresponds to, for example, an upper address and is activated during a plurality of memory operations. The sub-word lines correspond to, for example, lower addresses and are activated upon each of the memory operations. Activating the plurality of sub-word lines in succession can operate all the memory cells that are selectable by the activated main-word line. That is, consecutive accesses typically referred to as page operations can be performed in a wider memory region.
According to another aspect of the present invention, the word line includes a main-word line and a plurality of sub-word lines branching off from this main-word line, the sub-word lines being connected to the transfer switches of the memory cells. The main-word line and the sub-word lines are activated during a plurality of memory operations. Performing page operations without inactivating the sub-word lines allows a reduction in the power consumption of a control circuit for the sub-word lines. That is, the power consumption during operations can be reduced further.
According to another aspect of the present invention, the word line includes a main-word line and a plurality of sub-word lines branching off from this main-word line, the sub-word lines being connected to the transfer switches of the memory cells. The main-word line is activated in accordance with the address signal supplied along with the first command. The sub-word lines are activated in accordance with the address signal supplied along with at least one of the commands except the first command. The pre-activation of the main-word line can reduce the period between the supply of the second command to the activation of the sub-word lines. As a result, page operations can be performed at high speed. Besides, if there is any redundancy circuit for relieving the memory cells and the like, a relief judgment can be performed at high speed. Moreover, if redundancy is given on a main-word-line basis, a relief judgment can be performed in between an active command and a rise of the main-word line so that the judging time of the redundancy circuit is included into the operating time of other circuits. That is, the operation of the redundancy circuit can be prevented from becoming critical.
According to another aspect of the present invention, a plurality of bit lines are respectively connected to the plurality of memory cells connected to the sub-word lines. A precharging circuit for setting the bit lines to a predetermined voltage releases a part of the bit lines from a precharge operation in accordance with the address signal supplied along with the first command. Thus, the release of the precharge operation at an earlier time of memory operation can reduce the time taken for the supply of the first command to the completion of a read or write operation.
According to another aspect of the present invention, a plurality of memory blocks having the memory cells are composed of a plurality of segments. The precharging circuit releases the bit lines from a precharge operation with respect to each of the segments. This can decrease the number of circuits to be operated in read and write operations, which reduces the power consumption during operation.
According to another aspect of the present invention, one of a plurality of memory blocks having the memory cells is selected in accordance with the address signal supplied along with the first command. Selecting a memory block at an earlier time of memory operation can decrease the number of circuits to start operation in response to the second and subsequent commands. As a result, the time taken for the supply of the first command to the completion of a read or write operation can be reduced. That is, it is possible to achieve a speedup while maintaining the characteristic of low power consumption.
According to another aspect of the present invention, the memory blocks are composed of a plurality of segments. A plurality of bit lines are respectively connected to the plurality of memory cells connected to the sub-word lines. A plurality of sense amplifiers are formed commonly for a pair of memory blocks, and amplify data on the bit lines within the blocks. That is, the sense amplifiers each are supplied with a single memory block. A plurality of bit line selecting switches establish connections between the bit lines of each memory block and the sense amplifiers, respectively. The bit line selecting switches are selected with respect to each of the segments, in accordance with the address signal supplied along with the first command. Therefore, the connections between the bit lines of a memory block to be operated and sense amplifiers can be established at an earlier time of memory operation. In other words, the bit lines of memory blocks not to be operated and sense amplifiers can be disconnected. As a result, the time taken for the supply of the first command to the completion of a read or write operation can be reduced.
Since the bit lines and the sense amplifiers are connected segment by segment, the number of circuits to be operated in read and write operations can be decreased for a reduction in the power consumption during operations.
According to another aspect of the present invention, a refresh operation for rewriting data retained in the volatile memory cells is performed by selecting the bit line switches in a plurality of segments at once. More segments can be operated during refresh than in read and write operations, which reduces the number of times of refresh necessary for refreshing all the memory cells. Accordingly, refresh intervals can be extended to increase the ratio of read and write operations within a predetermined period. This means an improvement in I/O bus occupation rate (data transmission rate).
According to another aspect of the present invention, a decoder generates a decoding signal for selecting one of the sub-word lines in accordance with the address signals. An activation control circuit activates the decoder in response to the second command alone. The activation control circuit will not respond to the third and subsequent commands. Accordingly, the sub-word lines selected in response to the second command are also valid for the third and subsequent commands. Among the address signals supplied along with the third and subsequent commands, address signals for selecting sub-word lines are ignored. This can surely prevent the semiconductor memory from malfunctions such as multiple selection of word lines. The decoder can be reduced in power consumption since it performs no operation in response to the third and subsequent commands.
According to another aspect of the present invention, in a refresh operation for rewriting data retained in the volatile memory cells, the main-word line and the sub-word lines are selected in accordance with the address signal corresponding to the first command. This allows a start of a refresh operation in response to the first command so that the refresh operation can be performed faster than read and write operations. Accordingly, within a predetermined period, the ratios of read and write operations can be increased to improve the I/O bus occupation rate (data transfer rate).
According to another aspect of the present invention, the semiconductor memory includes a refresh occurring circuit, a buffer, and a refresh control circuit. The refresh occurring circuit generates at predetermined intervals a refresh request for refreshing the memory cells. The buffer holds the refresh request. The refresh control circuit performs a refresh operation based on the refresh request held by the buffer when the memory operation is not in execution. This semiconductor memory has a sufficient period between the completion of the memory operation and the activation of word lines for the next memory operation. In accordance with the refresh request held by the buffer, a refresh operation can be performed in this period so that the refresh operation is performed without being recognized from exterior. That is, the refresh of the memory cells can be performed internally and automatically.
According to another aspect of the present invention, the semiconductor memory includes a plurality of buffers for alternately holding the refresh request. During page operations, no refresh operation can be performed even if refresh requests occur. For this reason, the maximum number of page operations is limited in accordance with a refresh period, or the interval at which a refresh request occur. Since refresh requests can be held as many as the buffers, it is possible to increase the maximum number of page operations.
According to another aspect of the present invention, the commands are supplied in synchronization with a clock signal. The refresh control circuit performs a refresh operation in synchronization with the clock signal which is supplied when the memory operation is not in execution. This facilitates the timing design of the circuits necessary for refresh control.